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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. b 01/20/03 is93c46a is93c56a is93c66a issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 1,024/2,048/4,096-bit serial electrically erasable prom february 2003 functional block diagram cs sk d in d out dummy bit r/w amps data register address register address decoder write enable high voltage generator instruction decode, control, and clock generation eeprom array 128/256/512x16 64/128/256/x8 instruction register features ? industry-standard microwire interface ? non-volatile data storage ? low voltage operation: vcc = 2.5v to 5.5v ? full ttl compatible inputs and outputs ? auto increment for efficient data dump user configured memory organization ? by 16-bit or by 8-bit hardware and software write protection ? defaults to write-disabled state at power-up ? software instructions for write-enable/disable enhanced low voltage cmos e 2 prom technology versatile, easy-to-use interface ? self-timed programming cycle ? automatic erase-before-write ? programming status indicator ? word and chip erasable ? chip select enables power savings durable and reliable ? 40-year data retention after 1m write cycles ? 1 million write cycles ? unlimited read cycles ? schmitt-trigger inputs industrial and automotive temperature grade description the is93c46a/56a/66a is a low-cost 1kb/2kb/4kb non-volatile, issi ? serial eeprom. it is fabricated using an enhanced cmos design and process. the is93c46a/56a/66a contain power- efficient read/write memory, and organization of either 128/256/512 bytes of 8 bits or 64/128/256 words of 16 bits. when the org pin is connected to vcc or left unconnected, x16 is selected; when it is connected to ground, x8 is selected. the is93c46a/56a/66a is fully backwards compatible with is93c46/56/66. an instruction set defines the operation of the devices, including read, write, and mode-enable functions. to protect against inadvertent data modification, all erase and write instructions are accepted only while the device is write-enabled. a selected x8 byte or x16 word can be modified with a single write or erase instruction. additionally, the two instructions write all or erase all can program the entire array. once a device begins its self-timed program procedure, the data out pin (dout) can indicate the ready/ busy status by raising chip select (cs). the self- timed write cycle includes an automatic erase- before-write capability. the device can output any number of consecutive bytes/words using a single read instruction.
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? pin configurations 8-pin jedec soic ?g? 8-pin jedec soic ?gr? pin descriptions cs chip select sk serial data clock d in serial data input d out serial data output org organization select nc not connected vcc power gnd ground instruction begins with a start bit of the logical ?1? or high. following this are the opcode (2 bits), address field (6, 7, 8, or 9 bits), and data, if appropriate. the clock signal may be held stable at any moment to suspend the device at its last state, allowing clock- speed flexibility. upon completion of bus communication, cs would be pulled low. the device then would enter standby mode if no internal programming is underway. read (read) the read instruction is the only instruction that outputs serial data on the d out pin. after the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (please note that one logical ?0? bit precedes the actual 8 or 16-bit output data string.) the output on d out changes during the low-to-high transitions of sk (see figure 3). low voltage read the is93c46a/56a/66a have been designed to ensure that data read operations are reliable in low voltage environ- ments. they provide accurate operation with vcc as low as 2.5v. auto increment read operations in the interest of memory transfer operation applications, the is93c46a/56a/66a has been designed to output a continuous stream of memory content in response to a single read operation instruction. to utilize this function, the system asserts a read instruction specifying a start location address. once the 8 or16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. the address will wrap around continu- ously with cs high until the chip select (cs) control pin is brought low . this allows for single instruction data dumps to be executed with a minimum of firmware overhead. applications the is93c46a/56a/66a is very popular in many high- volume applications which require low-power, low- density storage. applications using this device include industrial controls, networking, and numerous other consumer electronics. endurance and data retention the is93c46 a/56a/66a is designed for applications re- quiring up to 1m programming cycles (write, wrall, erase and eral). it provides 40 years of secure data retention without power after the execution of 1m program- ming cycles. device operations the is93c46a/56a/66a are controlled by a set of instructions which are clocked-in serially on the din pin. before each low-to-high transition of the clock (sk), the cs pin must have already been raised to high, and the din value must be stable at either low or high. each 1 2 3 4 8 7 6 5 cs sk d in d out vcc nc org gnd 1 2 3 4 8 7 6 5 nc vcc cs sk org gnd d out d in 1 2 3 4 8 7 6 5 cs sk d in d out vcc nc org gnd (rotated) 8-pin dip, 8-pin tssop
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? write all (wrall) the write all (wrall) instruction programs all registers with the data pattern specified in the instruction. as with the write instruction, the falling edge of cs must occur to initiate the self-timed programming cycle. if cs is then brought high after a minimum wait of 250 ns (t cs ), the d out pin indicates the ready/ busy status of the chip (see figure 6). write disable (wds) the write disable (wds) instruction disables all programming capabilities. this protects the entire device against acci- dental modification of data until a wen instruction is executed. (when vcc is applied, this part powers up in the write disabled state.) to protect data, a wds instruction should be executed upon completion of each programming operation. erase register (erase) after the erase instruction is entered, cs must be brought low. the falling edge of cs initiates the self-timed internal programming cycle. bringing cs high after a minimum of t cs , will cause d out to indicate the read/ busy status of the chip: a logical ?0? indicates programming is still in progress; a logical ?1? indicates the erase cycle is complete and the part is ready for another instruction (see figure 8). erase all (eral) full chip erase is provided for ease of programming. erasing the entire chip involves setting all bits in the entire memory array to a logical ?1? (see figure 9). write enable (wen) the write enable (wen) instruction must be executed before any device programming (write, wrall, erase, and eral) can be done. when vcc is applied, this device powers up in the write disabled state. the device then remains in a write disabled state until a wen instruction is executed. thereafter, the device remains enabled until a wds instruction is executed or until vcc is removed. (see figure 4.) (note: chip select must remain low until vcc reaches its operational value.) write (write) the write instruction includes 8 or 16 bits of data to be written into the specified register. after the last data bit has been applied to d in , and before the next rising edge of sk, cs must be brought low. if the device is write- enabled, then the falling edge of cs initiates the self- timed programming cycle (see wen). if cs is brought high, after a minimum wait of 250 ns (5v operation) after the falling edge of cs (t cs ) d out will indicate the ready/ busy status of the chip. logical ?0? means programming is still in progress; logical ?1? means the selected register has been written, and the part is ready for another instruction (see figure 5). the ready/ busy status will not be available if: a) the cs input goes high after the end of the self-timed programming cycle, t wp ; or b) simultaneously cs is high, din is high, and sk goes high, which clears the status flag. instruction set - is93c46a 8-bit organization 16-bit organization (org = gnd) (org = vcc) instruction start bit op code address (1) input data address (1) input data read 1 10 (a 6 -a 0 )? (a 5 -a 0 )? wen (write enable) 1 00 11xxxxx ? 11xxxx ? write 1 01 (a 6 -a 0 )(d 7 -d 0 ) (3) (a 5 -a 0 )(d 15 -d 0 ) (2) wrall (write all registers) 1 00 01xxxxx (d 7 -d 0 ) (3) 01xxxx (d 15 -d 0 ) (2) wds (write disable) 1 00 00xxxxx ? 00xxxx ? erase 1 11 (a 6 -a 0 )? (a 5 -a 0 )? eral ( erase all registers) 1 00 10xxxxx ? 10xxxx ? notes: 1. x = don't care bit. 2. if input data is not 16 bits exactly, the last 16 bits will be taken as input data. 3. if input data is not 8 bits exactly, the last 8 bits will be taken as input data.
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? instruction set - is93c56a 8-bit organization 16-bit organization (org = gnd) (org = vcc) instruction start bit op code address (1) input data address (1) input data read 1 10 x(a 7 -a 0 ) ? x(a 6 -a 0 )? wen (write enable) 1 00 11xxxxxxx ? 11xxxxxx ? write 1 01 x(a 7 -a 0 )(d 7 -d 0 ) (3) x(a 6 -a 0 )(d 15 -d 0 ) (2) wrall (write all registers) 1 00 01xxxxxxx (d 7 -d 0 ) (3) 01xxxxxx (d 15 -d 0 ) (2) wds (write disable) 1 00 00xxxxxxx ? 00xxxxxx ? erase 1 11 x(a 7 -a 0 ) ? x(a 6 -a 0 )? eral ( erase all registers) 1 00 10xxxxxxx ? 10xxxxxx ? instruction set - is93c66a 8-bit organization 16-bit organization (org = gnd) (org = vcc) instruction start bit op code address (1) input data address (1) input data read 1 10 (a 8 -a 0 )? (a 7 -a 0 )? wen (write enable) 1 00 11xxxxxxx ? 11xxxxxx ? write 1 01 (a 8 -a 0 )(d 7 -d 0 ) (3) (a 7 -a 0 )(d 15 -d 0 ) (2) wrall (write all registers) 1 00 01xxxxxxx (d 7 -d 0 ) (3) 01xxxxxx (d 15 -d 0 ) (2) wds (write disable) 1 00 00xxxxxxx ? 00xxxxxx ? erase 1 11 (a 8 -a 0 )? (a 7 -a 0 )? eral ( erase all registers) 1 00 10xxxxxxx ? 10xxxxxx ? notes: 1. x = don't care bit. 2. if input data is not 16 bits exactly, the last 16 bits will be taken as input data. 3. if input data is not 8 bits exactly, the last 8 bits will be taken as input data. notes: 1. x = don't care bit. 2. if input data is not 16 bits exactly, the last 16 bits will be taken as input data. 3. if input data is not 8 bits exactly, the last 8 bits will be taken as input data.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? absolute maximum ratings (1) symbol parameter value unit v gnd voltage with respect to gnd ?0.3 to +6.5 v t bias temperature under bias (industrial) ?40 to +85 c t bias temperature under bias (automotive) ?40 to +125 c t stg storage temperature ?65 to +150 c notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance symbol parameter conditions max. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 5 pf operating range range ambient temperature v cc industrial ?40c to +85c 2.5v to 5.5v automotive ?40c to +125c 2.7v to 5.5v or 4.5v to 5.5v
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? dc electrical characteristics t a = ?40c to +85c for industrial and ?40c to +125c for automotive. symbol parameter test conditions vcc min. max. unit v ol output low voltage i ol = 100 a 2.5v to 5.5v ? 0.2 v v ol1 output low voltage i ol = 2.1 ma 4.5v to 5.5v ? 0.4 v v oh output high voltage i oh = ?100 a 2.5v to 5.5v v cc ? 0.2 ? v v oh1 output high voltage i oh = ?400 a 4.5v to 5.5v 2.4 ? v v ih input high voltage 2.5v to 5.5v 0.7 x v cc v cc +1 v 4.5v to 5.5v 0.7 x v cc v cc +1 v il input low voltage 2.5v to 5.5v ?0.3 0.2 x v cc v 4.5v to 5.5v ?0.3 0.8 i li input leakage v in = 0v to v cc (cs, sk, d in ,org) 0 2.5 a i lo output leakage v out = 0v to v cc , cs = 0v 0 2.5 a notes: automotive grade devices in this table are tested with vcc = 2.7v to 5.5v and 4.5v to 5.5v. power supply characteristics t a = ?40c to +85c for industrial symbol parameter test conditions vcc min. typ. max. unit i cc 1 vcc read supply current cs = v ih , sk = 1 mhz 2.7v ? 40 100 a cmos input levels 5.0v ? 100 500 a i cc 2 vcc write supply current cs = v ih , sk = 1 mhz 2.7v ? 0.4 1 ma cmos input levels 5.0v ? 1.5 3 ma i sb standby current cs = v ih , sk = 0v 2.7v ? 0.4 2 a 5.0v ? 2 4 a power supply characteristics t a = ?40c to +125c for automotive symbol parameter test conditions vcc min. typ. max. unit i cc 1 vcc read supply current cs = v ih , sk = 1 mhz 2.7v ? 40 100 a cmos input levels 5.0v ? 100 500 a i cc 2 vcc write supply current cs = v ih , sk = 1 mhz 2.7v ? 0.4 1 ma cmos input levels 5.0v ? 1.5 3 ma i sb standby current cs = v ih , sk = 0v 2.7v ? 0.5 3 a 5.0v ? 4 8 a
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? ac electrical characteristics t a = ?40c to +125c for automotive symbol parameter test conditions vcc mi n. max. unit f sk sk clock frequency 2.7v to 5.5v 0 1 mhz 4.5v to 5.5v 0 2 mhz t skh sk high time 2.7v to 5.5v 500 ? ns 4.5v to 5.5v 250 ? ns t skl sk low time 2.7v to 5.5v 500 ? ns 4.5v to 5.5v 250 ? ns t cs minimum cs low time 2.7v to 5.5v 250 ? ns 4.5v to 5.5v 250 ? ns t css cs setup time relative to sk 2.7v to 5.5v 100 ? ns 4.5v to 5.5v 50 ? ns t dis din setup time relative to sk 2.7v to 5.5v 100 ? ns 4.5v to 5.5v 100 ? ns t csh cs hold time relative to sk 2.7v to 5.5v 0 ? ns 4.5v to 5.5v 0 ? ns t dih din hold time relative to sk 2.7v to 5.5v 100 ? ns 4.5v to 5.5v 100 ? ns t pd1 output delay to ?1? ac test 2.7v to 5.5v ? 400 ns 4.5v to 5.5v ? 250 ns t pd0 output delay to ?0? ac test 2.7v to 5.5v ? 400 ns 4.5v to 5.5v ? 250 ns t sv cs to status valid ac test 2.7v to 5.5v ? 250 ns 4.5v to 5.5v ? 250 ns t df cs to dout in 3-state ac test, cs=vil 2.7v to 5.5v ? 200 ns 4.5v to 5.5v ? 100 ns t wp write cycle time 2.7v to 5.5v ? 10 ms 4.5v to 5.5v ? 5ms notes: 1. c l = 100pf
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? ac electrical characteristics t a = ?40c to +85c for industrial symbol parameter test conditions vcc mi n. max. unit f sk sk clock frequency 2.5v to 5.5v 0 1 mhz 2.7v to 5.5v 0 1 mhz 4.5v to 5.5v 0 2 mhz t skh sk high time 2.5v to 5.5v 500 ? ns 2.7v to 5.5v 350 ? ns 4.5v to 5.5v 250 ? ns t skl sk low time 2.5v to 5.5v 500 ? ns 2.7v to 5.5v 350 ? ns 4.5v to 5.5v 250 ? ns t cs minimum cs low time 2.5v to 5.5v 500 ? ns 2.7v to 5.5v 250 ? ns 4.5v to 5.5v 250 ? ns t css cs setup time relative to sk 2.5v to 5.5v 100 ? ns 2.7v to 5.5v 50 ? ns 4.5v to 5.5v 50 ? ns t dis din setup time relative to sk 2.5v to 5.5v 100 ? ns 2.7v to 5.5v 100 ? ns 4.5v to 5.5v 100 ? ns t csh cs hold time relative to sk 2.5v to 5.5v 0 ? ns 2.7v to 5.5v 0 ? ns 4.5v to 5.5v 0 ? ns t dih din hold time relative to sk 2.5v to 5.5v 100 ? ns 2.7v to 5.5v 100 ? ns 4.5v to 5.5v 100 ? ns t pd1 output delay to ?1? ac test 2.5v to 5.5v ? 400 ns 2.7v to 5.5v ? 350 ns 4.5v to 5.5v ? 250 ns t pd0 output delay to ?0? ac test 2.5v to 5.5v ? 400 ns 2.7v to 5.5v ? 350 ns 4.5v to 5.5v ? 250 ns t sv cs to status valid ac test 2.5v to 5.5v ? 400 ns 2.7v to 5.5v ? 250 ns 4.5v to 5.5v ? 250 ns t df cs to dout in 3-state ac test, cs=vil 2.5v to 5.5v ? 200 ns 2.7v to 5.5v ? 200 ns 4.5v to 5.5v ? 100 ns t wp write cycle time 2.5v to 5.5v ? 10 ms 2.7v to 5.5v ? 10 ms 4.5v to 5.5v ? 5ms notes: 1. c l = 100pf
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? ac waveforms figure 2. synchronous data timing figure 3. read cycle timing sk d in d out cs t cs 0 dm d0 110an a0 * address pointer cycles to the next register * notes: to determine address bits an-a0 and data bits dm-do, see instruction set for the specific device. t skh t t css t skl t csh cs sk d in d out (read) d out (write) (wrall) (erase) (eral) status valid t dis t dih t pd0 t sv t pd1 t df t df
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? figure 5. write (write) cycle timing notes: 1. after the completion of the instruction (d out is in ready status) then it may perform another instruction. if device is in busy status (d out indicates busy status) then attempting to perform another instruction could cause device malfunction. 2. to determine address bits a n -a 0 and data bits d m -d 0 , see instruction set for specific device. sk d in d out cs 11 0ana0 t cs dm d0 busy ready t sv t df t wp sk d in d out = 3-state cs t cs 11 00 1 ac waveforms figure 4. synchronous data timing
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? figure 7. write disable (wds) cycle timing sk d in cs 10 0 t cs 00 d out = 3-state sk d in d out cs 11 0 t cs dm d0 busy ready t sv t wp 00 notes: 1. after the completion of the instruction (d out is in ready status) then it may perform another instruction. if device is in busy status (d out indicates busy status) then attempting to perform another instruction could cause device malfunction. 2. to determine data bits d m -d 0 , see instruction set for the appropriate device. ac waveforms figure 6. write all (wrall) timing
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? figure 9. erase all (eral) cycle timing sk d in d out cs 1 1 1 an-1 t cs a0 busy ready t sv t df t wp an notes: to determine data bits an - a0, see instruction set for the appropriate device. sk d in d out cs 0 10 t cs busy ready t sv t df t wp 1 0 ac waveforms figure 8. erase (register erase) cycle timing note for figures 8 and 9: after the completion of the instruction (d out is in ready status) then it may perform another instruction. if device is in busy status (d out indicates busy status) then attempting to perform another instruction could cause device malfunction.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. b 02/20/03 is93c46a is93c56a is93c66a issi ? ordering information automotive range: -40 o c to +125 o c speed voltage range order part no. package 1mhz 2.7v to 5. 5v is93c46a-3pa 300-mil plastic dip is93c46a-3gra soic jedec 1mhz 2.7v to 5. 5v is93c56a-3pa 300-mil plastic dip is93c56a-3gra soic jedec 1mhz 2.7v to 5. 5v is93c66a-3pa 300-mil plastic dip is93c66a-3gra soic jedec 2mhz 4.5v to 5.5v IS93C46A-PA 300-m il plastic dip is93c46a-gra soic jedec 2mhz 4.5v to 5.5v is93c56a-pa 300-m il plastic dip is93c56a-gra soic jedec 2mhz 4.5v to 5.5v is93c66a-pa 300-m il plastic dip is93c66a-gra soic jedec ordering information industrial range: -40 o c to +85 o c speed voltage range order part no. package 1mhz 2.5v to 5.5v is93c46a-3pi 300-mil plastic dip is93c46a-3gi soic (rotated) jedec is93c46a-3gri soic jedec is93c46a-3zi 169-mil tssop 1mhz 2.5v to 5.5v is93c56a-3pi 300-mil plastic dip is93c56a-3gi soic (rotated) jedec is93c56a-3gri soic jedec is93c56a-3zi 169-mil tssop 1mhz 2.5v to 5.5v is93c66a-3pi 300-mil plastic dip is93c66a-3gi soic (rotated) jedec is93c66a-3gri soic jedec is93c66a-3zi 169-mil tssop

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